vga port companion circuit PACVGA201 ?2010 scillc. all rights reserved. publication order number: may 2010 rev. 3 PACVGA201/d features ? seven channels of esd protection for all vga port connector pins ? meets iec-61000-4-2 level-4 esd requirements ( 8kv contact discharge) ? very low loading capacitance from esd protection diodes on video lines, 4pf typical ? ttl to cmos level-translating buffers with power down mode for hsync and vsync lines ? three power supplies fo r design flexibility ? compact 16-pin qsop package ? rohs compliant (lead-free) finishing applications ? esd protection and termination resistors for vga (video) port interfaces ? desktop pcs ? notebook computers ? lcd monitors product description the PACVGA201 provides seven channels of esd protection for all signal lines commonly found in a vga port. esd protection is implemented with current-steering diodes designed to safely handle the high surge currents encount ered with iec-61000-4-2 level-4 esd protection ( 8kv contact discharge). when a channel is subjected to an electrostatic discharge, the esd current pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated. separate positive supply rails are provided for the video, ddc_out and sync channels to facilitate interfacing with low-voltage video controller ics and to provide design flexibility in multiple-supply-voltage environments. an internal diode (d 1 , in schematic below) is provided such that v cc2 is derived from v cc3 (v cc2 does not require an external power supply input). in applications where v cc3 may be powered down, diode d 1 blocks any dc current path from the ddc_out pins back to the powered down v cc3 rail via the upper esd protection diodes. two non-inverting drivers provide buffering for the hsync and vsync signals from the video controller ic (sync_in1, sync_in2). these buffers accept ttl input levels and convert them to cmos output levels that swing between ground and v cc3 . when the pwr_up input is driven low, the sync outputs are driven low and the sync inputs can float: no current will be drawn from the vcc3 supply. the PACVGA201 is housed in a 16-pin qsop package with rohs compliant lead-free finishing.
PACVGA201 rev. 3 | page 2 of 8 | www.onsemi.com simplified electrical schematic video_1 video_2 video_3 v cc1 gnd sync_out2 gnd v cc2 v cc3 sync_out1 sync_in2 sync_in1 ddc_out2 ddc_out1 pwr_up r b r p gnd 3 4 5 6 9 10 11 13 1 8 2 7 12 14 sd2 16 sd1 15 d 1 t o p view 16-pin qsop 1 2 3 4 14 13 12 11 5 6 7 10 9 8 15 16 sd2 sd1 sync_out2 sync_in2 sync_out1 sync_in1 ddc_out2 v cc3 v cc1 video_1 video_2 video_3 gnd pwr_up ddc_out1 v cc2
PACVGA201 rev. 3 | page 3 of 8 | www.onsemi.com ordering information part numbering information pins package ordering part number 1 part marking 16 qsop PACVGA201qr pacvga 201qr note 1: parts are shipped in tape & reel form unless otherwise specified. pin descriptions pins(s) name description 1 v cc3 v cc3 supply pin. this is an isolated supply input for the two sync buffers and sd1 and sd2 esd protection circuits. 2 v cc1 v cc1 supply pin. this is an isolated supply pi n for the video_1, vi deo_2 and video_3 esd protection circuits. 3 video_1 video signal esd protection channel. this pin is typically tied one of the video lines between the vga controller device and the video connector. 4 video_2 video signal esd protection channel. this pin is typically tied one of the video lines between the vga controller device and the video connector. 5 video_3 video signal esd protection channel. this pin is typically tied one of the video lines between the vga controller device and the video connector. 6 gnd ground reference supply pin. 7 pwr_up enables the sync buffers when high. when pwr_up is low the sync outputs are forced low and the inputs can be floated. 8 v cc2 v cc2 supply pin. this is an isolated supply pin for the ddc_out1 and ddc_out2 esd protection circuits. internally, v cc2 is derived from the v cc3 input if the v cc2 input is not connected to a supply voltage. 9 ddc_out1 ddc_out1 esd protection channel. 10 ddc_out2 ddc_out2 esd protection channel 11 sync_in1 sync signal buffer input. connects to the vga controller side of one of the sync lines. 12 sync_out1 sync signal buffer output. connects to the video connector side of one of the sync lines. 13 sync_in2 sync signal buffer input. connects to the vga controller side of one of the sync lines. 14 sync_out2 sync signal buffer output. connects to the video connector side of one of the sync lines. 15 sd1 esd protection channel input. 16 sd2 esd protection channel input.
PACVGA201 rev. 3 | page 4 of 8 | www.onsemi.com specifications absolute maximum ratings parameter rating units v cc1 ,v cc2 and v cc3 supply voltage inputs [gnd - 0.5] to +6.0 v diode forward current (one diode conducting at a time) 20 ma dc voltage at inputs video_1, video_2, video_3 ddc_out1, ddc_out2 sync_in1, sync_in2 [gnd - 0.5] to [v cc1 + 0.5] [gnd - 0.5] to [v cc2 + 0.5] [gnd - 0.5] to [v cc3 + 0.5] v v v operating temperature range 0 to +70 c storage temperature range -65 to +150 c package power rating 750 mw
PACVGA201 rev. 3 | page 5 of 8 | www.onsemi.com electrical operating characteristics (see note 1) symbol parameter conditions min typ max units i cc1 v cc1 supply current v cc1 = 5.0v 10 a v cc3 = 5v; sync inputs at gnd or v cc3 ; pwr_up pin at v cc3 ; sync ouputs unloaded 10 a v cc3 = 5v; sync inputs at 3.0v; pwr_up pin at v cc3 ; sync ouputs unloaded 200 a i cc3 v cc3 supply current v cc3 = 5v; pwr_up input at gnd; sync ouputs unloaded 10 a v cc2 v cc2 pin open circuit voltage v cc2 voltage internally derived from v cc3 via diode d1; no external current drawn [v cc3 - 0.80] v v ih logic high input voltage v cc3 = 5v; note 2 2.0 v v il logic low input voltage v cc3 = 5v; note 2 0.8 v v oh logic high output voltage i oh = -4ma, v cc3 = 5.0v; note 3 4.4 v v ol logic low output voltage i ol = 4ma, v cc3 = 5.0v; note 3 0.4 v r b, r p resistor value pwr_up = v cc3 = 5.0v 0.5 1 2 m i in input current video_x pins hsync, vsync pins v cc1 = 5.0v; v in = v cc1 or gnd v cc3 = 5.0v; v in = v cc3 or gnd 1 1 a a c in input capacitance on video_1, video_2 and video_3 pins v cc1 = 5.0v; v in = 2.5v; measured at 1mhz v cc1 = 2.5v; v in = 1.25v; measured at 1mhz 4 4.5 pf pf t plh sync buffer l => h propagation delay c l = 50pf; v cc3 = 5.0v; input t r and t f 5ns 8 12 ns t phl sync buffer h => l propagation delay c l = 50pf; v cc3 = 5.0v; input t r and t f 5ns 8 12 ns t r, t f sync buffer output rise & fall times c l = 50pf; v cc3 = 5.0v; input t r and t f 5ns 7.0 ns v esd esd withstand voltage v cc1 = v cc2 = v cc3 = 5v; note 4 8 kv note 1: all parameters specified over standard ope rating conditions unless otherwise noted. note 2: these parameters apply only to sync_in1, sync_in2 and pwr_up. note 3: these parameters apply only to sync_out1 and sync_out2. note 4: per the iec-61000-4-2 international esd st andard, level 4 contact discharge method. v cc1 , v cc2 and v cc3 must be bypassed to gnd via a low impedance ground plane with a 0.2uf or greater, low inductance, chip ceramic capacitor at each supply pin. esd pulse is applied between the applicabl e pins and gnd. esd pulse can be positive or negative with respect to gnd. applicable pins are: video_1, video_2, video_3, sync_out1, sd1, sync_out2, sd2, ddc_out1 and ddc_out2. all other pins are esd protected to the industry standard 2kv per the human body model (mil-std-883, method 3015).
PACVGA201 rev. 3 | page 6 of 8 | www.onsemi.com application information figure 1. typical connection diagram a resistor may be necessary between the v cc2 pin and ground if protection against a stream of esd pulses is required while the PACVGA201 is in the power-down state. the value of this resistor should be chosen such that the extra charge deposited into the v cc2 bypass capacitor by each esd pulse will be discharged before the next esd pulse occurs. the maximum esd repetition rate specified by the iec-61000-4-2 standard is one pulse per second. when the PACVGA201 is in the power-up state, an internal dischar ge resistor is connected to ground via a fet switch for this purpose. for the same reason, v cc1 and v cc3 may also require bypass capacitor di scharging resistors to ground if there are no other components in the system to provide a discharge path to ground.
PACVGA201 rev. 3 | page 7 of 8 | www.onsemi.com mechanical details qsop mechanical specifications PACVGA201 devices are supplied in 16-pin qsop packages. dimensions are presented below. for complete information on the qsop-16, see t he california micro devices qsop package information document. package dimensions package qsop (jedec name is ssop) pins 16 millimeters inches dimensions min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.81 3.98 0.150 0.157 e 0.64 bsc 0.025 bsc h 5.79 6.19 0.228 0.244 l 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs controlling dimension: inches * this is an approximate number which may vary. package dimensions for qsop-16
PACVGA201 rev. 3 | page 8 of 8 | www.onsemi.com on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any pr oduct or circuit, and specific ally disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or spec ifications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not de signed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reason able attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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